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In the mapping process each FECFRAME is serial-to-parallel converted, with a parallelism
level m = 2 for QPSK, 3 for 8PSK, 4 for 16APSK and 5 for 32APSK. Each parallel sequence
will be mapped into a constellation, generating a (I,Q) sequence of variable length depending
on the selected modulation efficiency. The input sequence is a FECFRAME, the output
sequence is a XFECFRAME (compleX FECFRAME), composed of 64800 /
m (normal
XFECFRAME) or 16200 / m (short XFECFRAME) modulation symbols. Each modulation
symbol is a complex vector in the format (I,Q) (I is the in-phase component and Q is the
quadrature component). These four different types of bit mapping into constellations can be
seen in Figure 4.11.
In the next step this XFECFRAME will be partitioned into fixed-length frames (cells or
named here as slots) of 90 symbols. Now this generated Physical-Layer Frame (PLFRAME)
consists of an additional Physical-Layer Header (PLHEADER) and a number of S slots (the
payload) - see Figure 4.12.
Fig. 4.12: Physical-Layer Framing (PLFRAME) [EN 302 307]
Now the PLHEADER itself consists of a so-called Start-of-Frame (SOF) sequence (26
symbols) and a Physical-Layer Signaling Code (PLSCODE) of 64 symbols. Amongst others
the PLSCODE consists of MODCOD (5 symbols), identifying the XFECFRAME modulation
type & FEC code rate pairs (assignment see Table 4.4); and TYPE (2 symbols) – the MSB
identifying the FECFRAME length (0=normal or 1=short).
Tab. 4.4: PLHEADER: MODCOD definitions [EN 302 307]
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